MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641114424 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 24, 2026, for An Energy-Efficient 8-Bit Wallace Tree Multiplier Using Pulse Boost And Modified Positive Feedback Adiabatic Logic For Nanoscale Cmos Applications.
Inventor includes Dr. L. Dharma Teja.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0032] This work introduces the design, implementation, and comparative analysis of an 8-bit Wallace Tree Multiplier based on two low-power logic styles Pulse Boost Logic (PBL) and Modified Positive Feedback Adiabatic Logic (MPFAL) in a 45nm CMOS technology node. The Wallace Tree architecture with its high arithmetic operation speed is optimized in this work to satisfy the performance and energy efficiency requirements of contemporary VLSI applications like digital signal processing and cryptography. The project overcomes critical limitations of traditional Static CMOS logic, such as high dynamic power dissipation and leakage problems at nanometer-scale technologies, by implementing other energy-efficient logic families. Pulse Boost Logic, with its double-phase clock-driven evaluation mechanism, enhances switching speed while reducing short-circuit power. MPFAL, meanwhile, uses charge recovery methods and a four-phase power-clock system to significantly cut down energy loss during circuit transition. Both multiplier topologies were created, simulated, and verified with LTSpice and Cadence Capture. Designs based on PBL exhibited high-speed performance, operating at frequencies approaching 1 GHz with lower dynamic power, while the MPFAL-based design had ultra-low average power consumption (123 µW) at a reasonable frequency of 2 MHz, indicating its potential for battery-powered and energy-limited applications.
Disclaimer: Curated by HT Syndication.
