MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641074763 A) filed by Madhankumar C; Dr. Pramod P; Dr. Resmi R; Dr. Sajan Jerome; Dr. Anu Babu; Dr. Baiju P. S; and Dr. Anil Kumar E. N on June 17, 2026, for An Energy Aware Fir Filtering Technique Using Adaptive Retiming And Deep Pipeline Scheduling.
Inventors include Dr. Pramod P; Dr. Resmi R; Dr. Sajan Jerome; Dr. Anu Babu; Dr. Baiju P. S; and Dr. Anil Kumar E. N.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: An energy aware FIR filtering technique using adaptive retiming and deep pipeline scheduling ABSTRACT Finite Impulse Response (FIR) filters are fundamental components in modern digital signal processing systems and are extensively employed in wireless communications, biomedical devices, multimedia processing, radar systems, Internet of Things (IoT) platforms, and embedded computing applications. As the demand for real-time signal processing and energy-efficient hardware continues to increase, conventional FIR filter architectures face significant challenges related to high power consumption, increased latency, excessive resource utilization, and limited scalability in high-speed applications. These limitations become more critical in battery-operated and resource-constrained systems where computational efficiency and energy optimization are primary design objectives. To address these challenges, this work proposes “An Energy-Aware FIR Filtering Technique Using Adaptive Retiming and Deep Pipeline Scheduling.” The proposed technique introduces an intelligent FIR filter architecture that combines adaptive retiming strategies with multi-stage deep pipeline scheduling to achieve high-throughput processing while minimizing energy consumption. The adaptive retiming mechanism dynamically relocates register positions across the filter structure based on signal activity, critical path analysis, and workload conditions, thereby reducing propagation delays and balancing computational loads. Simultaneously, the deep pipeline scheduling framework partitions filter operations into optimized processing stages, enabling parallel execution and efficient utilization of hardware resources. The proposed architecture incorporates a real-time energy monitoring and optimization module that continuously evaluates switching activity, processing demand, clock utilization, and data flow characteristics. Based on these parameters, the scheduling controller dynamically adjusts pipeline depth, processing frequency, and register allocation to maintain an optimal trade-off between performance and power consumption. Furthermore, intelligent resource management algorithms are employed to minimize redundant computations and reduce dynamic power dissipation without affecting filtering accuracy. Experimental evaluation is expected to demonstrate significant improvements in energy efficiency, throughput, latency reduction, clock frequency optimization, and hardware utilization when compared with conventional FIR filtering approaches. The proposed technique is particularly suitable for deployment in low-power embedded systems, wireless sensor networks, biomedical signal processors, software-defined radios, edge computing devices, IoT platforms, and next-generation communication systems. This work contributes a novel energy-aware digital signal processing methodology that integrates adaptive retiming and deep pipeline scheduling to enable high-performance, low-power, and scalable FIR filtering architectures for future intelligent electronic systems.
Disclaimer: Curated by HT Syndication.
