MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115504 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for An Efficient Fpga-Based Fir Filter Using Bram, Booth Multiplier, And Optimized Adder Architectures.
Inventor includes Dr. P. Kishore.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0022] This invention explores the design of Finite Impulse Response (FIR) filters, utilizing advanced adder and multiplier architectures along with folding techniques to enhance performance. The design incorporates several sophisticated arithmetic components, including the Carry-Save Adder (CSA) for efficient multi-operand addition, the Carry Skip Adder to speed up carry propagation, the Carry-Select Adder for reduced delay through precomputed carry values, and the high- speed Kogge-Stone Adder for rapid carry generation. Block RAM (BRAM) is employed for efficient data storage, while Booth's Multiplier is used for effective handling of signed numbers and reduction of partial products. The application of folding techniques further optimizes the FIR filter design by improving resource utilization and overall performance. This approach aims to produce a robust FIR filter capable of managing complex operations with enhanced efficiency and precision.
Disclaimer: Curated by HT Syndication.
