MUMBAI, India, Sept. 14 -- Intellectual Property India has published a patent application (202641106170 A) filed by Amrita Vishwa Vidyapeetham on September 03, 2026, for An Apparatus For Kernel Execution.
Inventors include Tipparaju, Srinivasa Sudhakar; Hegde, Ganapathi; and Chinnusamy, Paramasivam.
The application for the patent was published on September 11, 2026, under issue no. 37/2026.
Abstract: Embodiments of the present disclosure relate to an apparatus (100) for kernel execution. The apparatus (100) comprises a Semantic-Decoded Processing Element (SD- PE) for executing complete compute kernel operations within a heterogeneous RISC-V architecture. A network interface (106) receives a semantic descriptor (104) from a host processor (102), and a semantic decoder (108) decodes a corresponding semantic opcode. A Kernel Mapping Table (KMT) (108-4) maps the semantic opcode to a start address of a microcode kernel stored in a Writable Instruction RAM (WIRAM) (110). A local execution pipeline (112) executes the selected microcode kernel. One or more hardware execution contexts (112-2) and a hardware context switching unit (118) support program-counter-based context switching. A three-phase execution controller (124) coordinates kernel preparation, data preparation, and execution, while parallel DMA engines transfer operands to one or more local data buffer banks (122) for processing.
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