MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641111022 A) filed by Pragati Engineering College on September 16, 2026, for Ai-Based Predictive Power Optimization System For Digital Logic Circuits.
Inventors include Dr. Kola Satyanarayana; Dr. V. Anantha Lakshmi; Mr. M. Brahmaraju; and Dr. Chandra Sekhar Koppireddy.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: A system for dynamically reducing power consumption in digital logic circuits using an AI-based predictive power-state optimization system is disclosed, which preserves a necessary level of performance in a computational operation. The system tracks and saves operation information for temporally ordered digital logic blocks and is able to calculate patterns of workload from operation sequences, repetition periods, activity times and periods without activity. The extracted information is fed into an artificial-intelligence based prediction unit, which then predicts an upcoming computational workload, and an estimated duration of the predicted condition. An adaptive state-selection unit calculates the power-performance operating states that are available, depending on the predicted workload and expected duration, the energy requirement for entering and exiting each state, the timing of the transitions between states, and the expected energy savings. The evaluation results allow to choose the appropriate operating state for the respective digital logic block. It can be normal operation, reduced power operation, clock-controlled, frequency adjusted, voltage adjusted or a deeper low-power condition. A power-control unit implements selected state with functional and timing requirements. A feedback mechanism then compares reality of the load, power response, transition overhead and operating performance to the predicted load condition. This information is then fed back into further workload predictions and power state decisions. Such a system implements a predictive and adaptive power management mechanism which does not always require to rely on the traditional enable or reactive power management techniques. The architecture may be used for adder, multipliers, counters, registers, multiplexers, comparators, processing units and other digital logic circuits with varying computational requirements that are dynamically changing.
Disclaimer: Curated by HT Syndication.
