MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202641101021 A) filed by Onteru Anjaneyulu; and C V Krishna Reddy on August 21, 2026, for Advances In Vlsi Testability: Design Techniques For Manufacturable And Reliable Circuits.
Inventors include Onteru Anjaneyulu; and C V Krishna Reddy.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: The present invention relates to the development of a new DFT methodologies that increase fault detection and diagnosis capabilities, and at the same time decrease hardware overhead and testing time. The presented methodology uses scan-based architectures, BIST schemes, boundary scan, fault tolerant design approaches, and smart test algorithms to increase testability and robustness of circuits. Fault prediction by machine learning and adaptive testing can increase defect detection capability and reliability evaluation during all stages of product lifecycle. The methodology provides the possibility of effective testing of SoC designs. It decreases the costs of manufacturing and increases reliability of products. FIG.1
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