MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202621083946 A) filed by Indian Institute Of Technology Indore on July 08, 2026, for A Unified Multi-Precision Floating-Point Simd Fused Multiply-Accumulate Architecture And Method For Adaptive Image Processing.
Inventors include Mohd Faisal Khan; Mukul Lokhande; and Dr. Santosh Kumar Vishvakarma.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: A UNIFIED MULTI-PRECISION FLOATING-POINT SIMD FUSED MULTIPLY-ACCUMULATE ARCHITECTURE AND METHOD FOR ADAPTIVE IMAGE PROCESSING The invention relates to digital arithmetic hardware for adaptive image processing, and more particularly to a unified multi-precision floating-point SIMD fused multiply-accumulate architecture and method supporting FP4 E3M0, FP4 E2M1, FP6 E3M2, and FP8 E5M2 formats. Operands A, B, and C are received by an Input Formatter and classified by an Input Precision Decoder, whereupon a Mode Controller selects 2 x FP4 operations per cycle, 1 x FP6 operation per cycle, or 1 x FP8 operation per cycle. A Shared Exponent Unit is reconfigured for dual 3-bit SIMD exponent processing or single 6-bit exponent processing, while a Reconfigurable Multiplier Hierarchy selectively provides exponent-domain MAC without mantissa multiplication, or 2 x 2, 4 x 4, and 6 x 6 mantissa multiplication. A Fused Multiply-Accumulate Unit, together with an Alignment and Normalization Unit and an Output Formatter, executes fused A x B + C computation with mode-dependent alignment, rounding, normalization, and result reconstruction for adaptive precision assignment across image regions.
Disclaimer: Curated by HT Syndication.
