MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641112786 A) filed by Dr. S. Abirami; Dr. V. Senthilkumar; Dr K. Venkatesan; Dr. K. Lakshmiprabha; Dr. M. Andal; Dr. T. Manimozhi; Mrs. K. Salai Aranganayaki; Mrs. N. Jegajothi; Ms. M. Abinayasri; and Ms. V. Kamala Vaishnavi on September 21, 2026, for A Systematic For Vedic Mathematics Based Computer Operation Of Arithmetic Operation.
Inventors include Dr. S. Abirami; Dr. V. Senthilkumar; Dr K. Venkatesan; Dr. K. Lakshmiprabha; Dr. M. Andal; Dr. T. Manimozhi; Mrs. K. Salai Aranganayaki; Mrs. N. Jegajothi; Ms. M. Abinayasri; and Ms. V. Kamala Vaishnavi.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: The present invention relates to the development of a systematic methodology for the implementation of Vedic Mathematics, which is an ancient mathematics system of India, for improving computer arithmetic operations. Through the use of the particular sutras in Vedic Mathematics like Urdhva Tiryakbhyam for multiplication and Nikhilam for subtraction, the system improves on the design of logic circuits. The system uses parallel processing of bits which results in lower propagation delays than the currently used array multipliers. This paper discusses the analysis of the implementation of Vedic based logic circuits and its benefits. The technique offers improved performance and reduced chip area of the hardware. Therefore, incorporation of these time-saving methodologies into computer arithmetic units is possible through digital engineering. FIG.1
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