MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202541030059 A) filed by Bharat Electronics Limited on March 28, 2025, for A System For Robust And Low Computational Complexity Receiver Of Hub System In A Mf-Tdma Network.
Inventors include Priyadarshini M P; Lotiswar Borman; and Nidhi Srivastava.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT A SYSTEM FOR ROBUST AND LOW COMPUTATIONAL COMPLEXITY RECEIVER OF HUB SYSTEM IN A MF-TDMA NETWORK The objective of the present invention is to propose a novel scheme for robust and low computational complexity receiver of Hub System in a MF-TDMA network. Hub system in a MF-TDMA network continuously broadcasts the bandwidth and time-slot information in TDM mode, while all the RCST operate in TDMA mode, wherein each RCST operates in a different channel bandwidth. Therefore, the Hub system receives data from multiple RCSTs at different time slots with each RCST operating at different channel bandwidth. The proposed receiver system for Hub efficiently processes the data received from all the RCSTs operating at different bandwidth and different time slots with reduced computational complexity. Samples received from ADC are passed to multi-stage filter bank that splits the signal into narrow bandwidth sub-bands. Further, the data from the sub-bands are passed on to bank of Time-Slot Frame Buffers (TSFB), wh
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