Intellectual Property India Publishes Patent Application for A System Comprising Of Reconfigurable Compute-In-Memory Circuit With An On-Chip, Optimised Bit-Width And Voltage-Frequency Parameter Controller For Accelerating Artificial Intelligence Algorithms

MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641113892 A) filed by Dr. N. Chinna Alluraiah; Dr. Syed Suraya; Kante Ramesh; Y. Madhusudhana; Andhi Radha; K Srinivasa Rao; Avilala Rajasekhar Yadav; Polukallu Surya Prakash Reddy; P. Harish Kumar; and Dr. S. Kannappan on September 23, 2026, for A System Comprising Of Reconfigurable Compute-In-Memory Circuit With An On-Chip, Optimised Bit-Width And Voltage-Frequency Parameter Controller For Accelerating Artificial Intelligence Algorithms.

Inventors include Dr. N. Chinna Alluraiah; Dr. Syed Suraya; Kante Ramesh; Y. Madhusudhana; Andhi Radha; K Srinivasa Rao; Avilala Rajasekhar Yadav; Polukallu Surya Prakash Reddy; P. Harish Kumar; and Gunturu Jyothi.

The application for the patent was published on October 02, 2026, under issue no. 40/2026.

Abstract: A system for accelerating artificial intelligence algorithms comprises a reconfigurable compute-in-memory circuit comprising a bit-scalable multiply-accumulate array operable at a dynamically selectable bit-width, and a dynamic voltage and frequency scaling unit supplying the reconfigurable compute-in-memory circuit with a dynamically selectable voltage and clock frequency. A layer sensitivity register bank stores, for each algorithm layer, a coefficient relating numerical precision to accuracy degradation. An on-chip parameter optimisation controller, triggered at each layer boundary, computes an optimised bit-width, voltage, and frequency using a marginal-utility cost function relating the sensitivity coefficient, an energy cost model, and a remaining budget, allocating incremental parameter adjustments in order of greatest reduction in accuracy degradation per unit energy cost until the budget is exhausted. An energy/latency monitor measures actual energy and delay per layer and updates the remaining budget for subsequent layers. This on-chip, closed-loop, mathematically formulated joint bit-width and voltage/frequency optimisation improves energy efficiency and throughput relative to systems using a fixed or externally configured operating bit-width, voltage, or frequency.

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