MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202641076433 A) filed by Manipal Academy Of Higher Education on June 19, 2026, for A System And Method For Streaming Neural Inference Acceleration On A Reconfigurable Logic Fabric.
Inventors include Sai Vishal Setti; and Vakkalakula Bharath Sreenivasulu.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: The invention discloses a streaming dataflow transformation architecture for neural inference acceleration on a reconfigurable logic fabric. The architecture comprises a data ingress interface, a clock domain crossing synchronization circuit, a dataflow transformation engine, a wavefront scheduling engine, and a weight-stationary systolic compute array. A deterministic mapping function executed within a single combinational decode stage concurrently encodes spatial routing and temporal phase alignment for each received data unit without intermediate Block RAM or Direct Memory Access staging. The dataflow transformation engine and wavefront scheduling engine are co-instantiated within a continuous register-transfer pipeline, enabling temporally serialized wireless ingress data to be transformed inline and routed directly to processing element inputs at the clock cycle of data arrival. The architecture eliminates intermediate memory staging entirely from the inference ingestion pipeline, achieving sub-microsecond inference initiation latency on resource-constrained field-programmable gate array fabrics. (FIG. 2)
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