MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202621067911 A) filed by Indian Institute Of Technology Indore on May 30, 2026, for A System And Method For Sram Compute-In-Memory Multiply-Accumulate Using Regime-Controlled Fixed Posit(8,2) Mechanism.
Inventors include Mohd Faisal Khan; Pratham Sharma; and Santosh Kumar Vishvakarma.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: ABSTRACT A SYSTEM AND METHOD FOR SRAM COMPUTE-IN-MEMORY MULTIPLY-ACCUMULATE USING REGIME-CONTROLLED FIXED POSIT(8,2) MECHANISM The invention relates to a SRAM-based system and method for multiply-accumulate using fixed Posit(8,2) representation. A posit input interface receives 8-bit operands, and a posit decoder decomposes each operand into sign, signed regime, exponent, fraction, and special-case indicators for storage in field-specific SRAM banks under a common logical address in a dual operand bank organization. During MAC execution, a sequencing controller coordinates concurrent field retrieval, while a regime controller derives compute-depth, total-shift, and arithmetic precision-control signals from regime and exponent fields. Hidden-bit insertion logic, a bit-serial fraction multiplier, sign logic, partial-product formatting logic, and an alignment unit generate aligned signed intermediate products for accumulation in a wide accumulator. A posit normalizer and encoder converts the accumulated fixed-point sum into an 8-bit Posit(8,2) output, enabling regime-controlled precision-scalable in-memory MAC execution with reduced multiplier complexity.
Disclaimer: Curated by HT Syndication.
