MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202621100406 A) filed by Prof. Mahendra S. Dalvi; Prof. Snehal H. Gorde; Prof. Ujjwala D. Deore; Prof. Aarti D. Nimse; Prof. Kavita Y. Sonawane; and Prof. Rita G. Patil on August 19, 2026, for A System And Method For Runtime Bypass Of Aging Interconnect Segments In A Network-On-Chip Using A Graph Neural Network.
Inventors include Prof. Mahendra S. Dalvi; Prof. Snehal H. Gorde; Prof. Ujjwala D. Deore; Prof. Aarti D. Nimse; Prof. Kavita Y. Sonawane; and Prof. Rita G. Patil.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: [064] The present invention provides a system and method for runtime bypass of aging interconnect segments in a network-on-chip (NoC). A plurality of routers are interconnected through physical interconnect segments, and condition-monitoring circuitry obtains runtime parameters indicative of physical conditions of the interconnect segments. Graph-state generation circuitry represents the routers as graph nodes and the interconnect segments as graph edges having condition-dependent attributes. A graph neural network inference engine processes the graph data using information associated with topologically related network elements and generates routing information indicative of an aging interconnect segment and an alternative communication path. Routing control circuitry modifies an output-port selection state of a router to restrict use of the aging interconnect segment and forward packets through an alternative physical interconnect segment. Routing-validation circuitry may validate an inferred routing state against physical connectivity and routing constraints. The system thereby provides pre-failure, condition-responsive redistribution of NoC packet traffic to reduce stress on progressively degrading interconnect segments. Accompanied Drawing [FIGS. 1-2]
Disclaimer: Curated by HT Syndication.
