MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202641101766 A) filed by Vellore Institute Of Technology on August 23, 2026, for A System And Method For Preemptive Cpu Resource Al Temporal Dependency Prediction.
Inventors include N. Krishnamoorthy; Rishil N; Shrishabarish G; and Prasanna Venkatesh S.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: A preemptive central processing unit resource allocation system (100) comprises a telemetry acquisition module, a temporal dependency graph generation module, a prediction module, a confidence evaluation module, a neuro-symbolic verification module, a digital twin verification module, a scheduler optimization module, a scheduling control module, and a feedback learning module. The telemetry acquisition module acquires process execution events to construct a cross-session temporal dependency graph. The prediction module predicts dependent process launches, while the confidence evaluation module generates confidence scores using historical execution information. The neuro-symbolic verification module evaluates predefined hardware safety constraints before scheduling. The digital twin verification module simulates processor allocation, cache behaviour, thermal characteristics, and memory utilization prior to execution. The scheduling control module invokes operating-system scheduling primitives for processor priority allocation and heterogeneous core assignment. The feedback learning module updates dependency confidence values and selectively restores scheduling parameters according to execution outcomes.
Disclaimer: Curated by HT Syndication.
