MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641113549 A) filed by Vellore Institute Of Technology on September 22, 2026, for A System And Method For Predictive Duration-Matched Physical-Qubit Allocation And Quantum-Circuit Execution.
Inventors include Sweta Bhattacharya; Abhinav Anand; Chirag Bansal; and Marmik Pradip Kaila.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: The present disclosure proposes a system (100) for predictive duration-matched physical-qubit allocation and quantum-circuit compilation. The system (100) comprises a computing device (102) having a processor (104) and a memory (106), and is operatively coupled to a gate-model quantum processor through quantum control hardware and communicatively coupled to a server (130) through a network (128). The processor (104) executes a plurality of modules (108) comprising a calibration- data acquisition module (110), a qubit-degradation forecasting module (112), an execution-duration estimation module (114), a qubit-risk and admissibility module (116), a coupling-map restriction module (118), and a compiler and transpiler module (120). The plurality of modules (108) predicts physical-qubit degradation over an execution duration, restricts the physical-qubit coupling map, remaps logical qubits, and generates a transpiled quantum circuit. The system (100) supports post- execution feedback recalibration and topology-aware correlated-degradation evaluation.
Disclaimer: Curated by HT Syndication.
