MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202641088917 A) filed by Presidency University on July 21, 2026, for A System And Method For Constraint-Driven Rtl Synthesis Of Low-Power Digital Systems.
Inventor includes Aruna M.
The application for the patent was published on July 31, 2026, under issue no. 31/2026.
Abstract: ABSTRACT A System and Method for Constraint-Driven RTL Synthesis of Low-Power Digital Systems The present invention discloses a system and method for constraint-driven register transfer level (RTL) synthesis of low-power digital systems. The method includes designing a digital circuit at RTL, simulating the circuit for functional verification, defining timing constraints including clock, input delay, and output delay constraints, and applying the constraints during synthesis. The system includes modules for constraint definition, synthesis, implementation, and analysis. The application of timing constraints enables reduction in switching activity, resulting in optimized power consumption without increasing hardware resource utilization. In an embodiment, an arithmetic logic unit (ALU) is implemented to demonstrate the effectiveness of the present invention. The synthesized design shows a significant reduction in power consumption while maintaining timing performance and area efficiency. The instant invention is applicable in VLSI design, AI processors, embedded systems, and electronic design automation tools for developing low-power digital circuits.
Disclaimer: Curated by HT Syndication.
