MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115381 A) filed by Sri Eshwar College Of Engineering on September 24, 2026, for A System And Method For Automated Memory Leak Detection Using Partial Call-Path Analysis, Variable Life-Cycle Tracking And Adaptive Path Merging.
Inventor includes C. Arunkumar.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: The proposed invention generates an Abstract Syntax Tree (AST) and/or Control Flow Graph (CFG) from the source code and identifies memory-relevant operations including allocation, assignment, usage, reference transfer, reassignment, scope transition and deallocation. Memory-relevant partial call paths are generated instead of exhaustively analysing all possible execution paths. The life cycle of each dynamically allocated memory resource is tracked across the identified paths and across function or module boundaries. The invention further performs inter-module dependency analysis to determine relationships associated with allocation, transfer, usage and deallocation of memory resources. Memory-relevant partial paths are compared based on characteristics including control-flow behaviour, memory-event sequence and variable dependencies. Similar paths satisfying a defined similarity criterion are adaptively merged into representative paths, thereby reducing redundant path analysis. The representative paths are analysed to determine whether each allocated memory resource reaches a valid deallocation state. A potential memory leak is identified when allocated memory remains unreleased, when a reference is reassigned before the associated memory is released, when a resource becomes unreachable due to a scope transition, or when an execution path terminates or bypasses the required deallocation operation.
Disclaimer: Curated by HT Syndication.
