MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202621058503 A) filed by Dr. Sheetal Bawane; Mr. Gaurav Matange; Dr. Swati Dhondiram Jadhav; Dr. Ooi Chee Pun; Dr. Tan Wooi Haw; Dr. Tan Yi Fei; Dr. Anurag Shrivastava; and Ravi Kalra on May 07, 2026, for A System And Method For A Microchip Layout Architecture For Low-Power Edge Computing Devices.
Inventors include Dr. Sheetal Bawane; Mr. Gaurav Matange; Dr. Swati Dhondiram Jadhav; Dr. Ooi Chee Pun; Dr. Tan Wooi Haw; Dr. Tan Yi Fei; Dr. Anurag Shrivastava; and Ravi Kalra.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: The present invention relates to a microchip layout architecture for edge computing devices. The architecture comprises a semiconductor substrate having a sensor interface zone, processing zone, accelerator zone, local memory zone, secure processing zone, communication interface zone, power management zone, and thermal regulation zone. The sensor interface zone is positioned near the processing zone and accelerator zone to reduce data transfer distance. The local memory zone is arranged between the processing zone and accelerator zone for low-latency access to sensor buffers, instructions, and model parameters. The secure processing zone includes cryptographic circuits, secure memory, and access-control logic in an isolated region. The power management zone provides independently controllable power islands for selective activation of functional blocks. The thermal regulation zone includes thermal vias, temperature sensors, and heat-spreading structures. The invention improves local processing speed, reduces power consumption, enhances hardware security, and enables reliable operation of compact edge devices. (Accompanied Figure No. 1-4)
Disclaimer: Curated by HT Syndication.
