MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641110360 A) filed by Vellore Institute Of Technology on September 15, 2026, for A Standalone Embedded System And Zero-Dependency Hardware-Firmware Architecture For Edge Electrophysiological Signal Processing.
Inventors include Sivakumar Rajagopal; and Riya Kulheri.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: ABSTRACT The present invention provides a standalone, zero-dependency embedded electrophysiological pattern recognition system implemented on a dual-core 32- bit microcontroller. The system receives Right Channel (RE1) and Left Channel (LE1) electrophysiological signals and performs element-wise binocular signal averaging, zero-imputation, fixed 256-point resampling, and min-max normalization within microcontroller memory. A native C++ neural matrix computation engine executes a three-layer feedforward neural network using statically compiled weight and bias arrays stored in non-transitory flash memory, thereby eliminating third- party runtime dependencies and dynamic memory allocation during inference. The neural architecture comprises approximately 8,769 parameters with a memory footprint of approximately 34.3 KB and provides an inference latency of approximately 186 ms. A configurable decision threshold controls GPIO-based visual indication. The system further provides an autonomous Soft-AP HTTP interface and USB serial mode for local data transfer and validation without cloud connectivity, enabling memory-efficient and autonomous edge-based electrophysiological classification.
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