MUMBAI, India, Sept. 7 -- Intellectual Property India has published a patent application (202641033711 A) filed by Srm Institute Of Science And Technology Tiruchirappalli on March 20, 2026, for A Selective-Activation Mechanism Low-Power Synchronous Random Access Memory Controller.
Inventors include Mohammed Shafeek A U; Ashwath M; and Dr. K Vaishnavi.
The application for the patent was published on September 04, 2026, under issue no. 36/2026.
Abstract: The invention reveals a low power synchronous RAM controller which uses a finite state machine to direct read and write operations. When no memory operation is requested the controller is in idle state whereby the RAM and related control signals are disconnected. When a read or write request is detected, the controller sets the corresponding state of operation and only allows the RAM to access it when the requested operation is in progress. After the operation is over, the controller goes back to the idle state and hence reduces any unnecessary power consumption. This selective enablement methodology is used to provide the memory access on-demand which means that power is highly saved but the proper synchronous behaviour is also maintained.
Disclaimer: Curated by HT Syndication.
