MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641114490 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 24, 2026, for A Resource-Efficient Fpga-Based Artificial Neural Network Architecture For Real-Time American Sign Language Recognition.
Inventor includes Dr. N. Neelima.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0026] American Sign Language (ASL) recognition has a fundamental role in enabling powerful communication among the hearing-impaired and the general public. This project suggests an efficient, hardware-accelerated ASL recognition system on the basis of a fully connected Artifical Neural Network(ANN) transmitted on the PYNQ-Z2 FPGA board, which is founded on the Xilinx Pynq-Z2 SoC. The design realizes many dense layers of Verilog HDL, synthesized using Xilinx Vivado, with isolated neuron and layer blocks structured for optimal parallelism and asset use. An AXI-Lite interface enables uniform integration with the Handling Framework in the PYNQ SoC, allowing high-level control and information management. The framework compares the utilize of ReLU and Sigmoid enactment capacities in terms of asset utilization, idleness, and control utilization. Results show that the ReLU-based demonstrate achieves significantly better execution with reduced rationale asset utilize and less energetic control on the FPGA texture. [0027] The entire design is tailor-made for real-time, low-power usage, making it ideal for edge devices. This application supports the feasibility and effectiveness of transmitting neural systems for ASL recognition on embedded hardware levels, advancing the possibility of convenient, accessible communication devices. Notably, there is a strong focus on resource utilization so as not to violate the performance standards set out for the design of the given FPGA. This focus is also on the optimization of the design. The solution performs well on diverse datasets, is robust to handedness and achieves competitive level of accuracy on sets of handwriting. The building blocks are designed in such a way that the structure is capable to accommodate development of more potent networks or support more characters with little amount of redesign work. In addition, the effective hardware implementation allows for such applications to be integrated or even real-time systems. There is a hardware implementation of an Artificial Neural Network (ANN) which uses Verilog and addresses the requirement for efficient embedded devices for edge computation scenarios. Potential users are mobile OCR devices, tools for assisting blind people and automatic data entering systems. Convolutional layers shall be added in order to increase the architecture and its application possibilities while another will include searching for the best way to minimize the loss of quantization caused in the hardware implementation. It is also important to note that there is much research hence more work needs to be done. The perspective of employing a combination of Verilog, FPGAs and Hardware acceleration to create neural networks for hand written letters recognition has been successfully illustrated. This is more apparent considering the need for simultaneity in recognition tasks, span accuracy and energy efficiency in real time.
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