MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115435 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for A Low-Power Reversible Pipelined Fir Filter Architecture For Real-Time Eeg Signal Noise Reduction.
Inventor includes Dr. Aytha Ramesh Kumar.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0029] The EEG signals face problems regarding noise such as muscle and external disturbances. EEG signals are very important in medicine for analyzing brain activity and diagnosing medical illness. Electroencephalogram (EEG) signals, which represent the electrical activity of the brain, are used in applications such as epilepsy diagnosis, sleep disorders, and brain injuries, as well as in brain-computer interfaces. Biomedical signal processing is a critical area of application in diagnosing and monitoring neurological conditions. However, the main drawback is its predominant presence of noise interference gradually decreases the data integrity. To overcome this, we incorporated a Reversible pipelined FIR filter structure combined with a Reversible Vedicmultiplier and a Reversible Carry Select Adder to increase efficiency. Reversible logic continues to capture the interest of emerging fields such as quantum computing and low-power VLSI design and nanotechnology, because it reduces energy dissipation successfully. The main reason for using a Reversible Vedic multiplier is based on the fact that it requires low power and also provides high-speed operations. The addition operations in the overall filter architecture are speeded up by the usage of a Reversible Carry Select Adder. MATLAB and Vivado 2022.2 are software tools used for simulation and synthesis. From simulation and synthesis, the proposed design reduces dynamic power consumption, quantity of latency,and increases efficiency. Hence the design is appropriate for real-time EEG processing.
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