MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115569 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for A Low-Power Dynamic Cmos Comparator With Integrated Leakage Control Techniques For High-Speed Applications.
Inventor includes Dr. K L V Ramana Kumari.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0027] This invention introduces a low-power dynamic CMOS comparator designed using 22nm and 45nm technology, operating at varying voltages. We employ circuit-level techniques such as ONOFIC (On-Off logic circuit), LCNT (Leakage Control NMOS transistor), and LCMT (Leakage Control Multi-threshold Transistors) to achieve optimal performance. Introducing leakage transistors within the pull-up and pull-down networks eliminates critical paths and significantly reduces leakage current compared to traditional designs. In addition to traditional CMOS technology, the techniques can be utilized for their superior control over short- channel effects and reduced leakage. By integrating LECTOR, GALEOR, ONOFIC, LCNT, and LCMT techniques with dynamic comparator, we achieve better subthreshold leakage control and overall performance. The comparator is evaluated for power consumption, delay, and power dissipation products showing significant improvements over existing designs, making it highly efficient for low-power, high-speed applications.
Disclaimer: Curated by HT Syndication.
