MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202611064320 A) filed by Noida Institute Of Engineering & Technology on May 21, 2026, for A Low-Jitter Clock Generation Circuit For Digital Systems.
Inventors include Dr. Vijay Kumar Pandey; and Dr. Vinod Mansiram Kapse.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: The invention discloses a low-jitter clock generation circuit for digital systems. The circuit includes a reference input conditioner, phase comparison unit, programmable loop filter, digitally assisted oscillator, isolated bias regulator, divider and feedback unit, jitter monitor, calibration controller, and output distribution stage. The calibration controller adjusts loop, oscillator, bias, duty cycle, and output parameters based on monitored timing variation and operating conditions. The circuit provides stable clock outputs with reduced jitter, controlled duty cycle, and improved resilience to supply, temperature, and load disturbances.
Disclaimer: Curated by HT Syndication.
