MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641078561 A) filed by Sr University on June 25, 2026, for A Hybrid Low-Power Architecture For A Binary Coded Decimal (bcd) Adder.
Inventors include Dr. Ts. Narayanamurthy; Dr. Ch. Rajendra Prasad; and Dr. Roseline Oluwaseun Ogundokun.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: A HYBRID LOW-POWER ARCHITECTURE FOR A BINARY CODED DECIMAL (BCD) ADDER The present invention relates to a hybrid low-power architecture for Binary Coded Decimal (BCD) adders that integrates power gating, clock gating, and multi- VDD techniques under a unified control framework. The architecture comprises control logic, a BCD adder core, power-gating switches, a clock-gating unit, and multiple voltage domains. The control logic dynamically monitors input activity, carry conditions, and operational states to selectively activate computational resources only when required. Power gating disconnects the adder core during idle periods to reduce leakage currents, while clock gating suppresses unnecessary clock transitions to minimize dynamic power consumption. Multi-VDD operation assigns higher supply voltage to timing-critical blocks and lower supply voltage to non- critical correction logic. The coordinated operation of these techniques significantly reduces dynamic and static power dissipation while maintaining arithmetic accuracy, performance, reliability, and scalability, making the architecture suitable for low-power VLSI applications.
Disclaimer: Curated by HT Syndication.
