MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202641085139 A) filed by Pradeep K B; Praseetha K B; Nisha K B; and Smitha K B on July 11, 2026, for A Hybrid Geometric-Boolean Digital Logic Architecture And Canonical Decomposition Engine For Low-Power, High-Speed Computing.
Inventors include Pradeep K B; Praseetha K B; Nisha K B; and Smitha K B.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: A Hybrid Geometric-Boolean Digital Logic Architecture and Canonical Decomposition Engine for low-power, high-speed computing. The Architecture partitions an N- bit input vector into a higher-order bit field and a lower-order bit field at a Primitive Boundary Interface. The higher-order bit field is mapped as hexadecimal coordinate pairs onto a Base-16 Geometric Macro-Grid and resolved through a Geometric Multiplexer (MUX) Topology via hardwired spatial wire-routing, eliminating dynamic transistor switching power for the bulk of the bit-width. The lower-order bit field is concurrently and independently resolved through conventional Boolean Logic Cells with full bit-level precision. A Canonical Decomposition Engine orchestrates both resolution paths and combines their outputs at a spatial summation node to produce a bit-exact final result compatible with existing digital logic standards. The Architecture is recursively extensible to synchronous adders, subtractors, parallel multipliers, division matrices, factorisation units, and all standard derived Boolean gates—AND, OR, XOR, XNOR—and maps natively onto both FPGA and ASIC silicon fabrics, enabling substantial reductions in dynamic power consumption and propagation delay without sacrificing arithmetic precision or downstream hardware compatibility.
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