MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202611058543 A) filed by Krishan Kumar; Chandigarh University; and Syyada Shumaila Khurshid on May 07, 2026, for A High-Performance 32-Bit Risc Processor Using Vedic Arithmetic For Enhanced Speed And Power Efficiency.
Inventors include Dr. Krishan Kumar; Jasdeep Kaur; Dr. Monika Kalra; Dr. Kiran Utreja; Rikendra; Dr. Sangeeta Kumari; and Dr. Vikas Garg.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: The present invention relates to a high-performance 32-bit Reduced Instruction Set Computer (RISC) processor incorporating Vedic arithmetic techniques to improve computational speed, reduce power consumption, and minimize critical path delay. The processor integrates a Vedic multiplier and a Vedic Multiply-Accumulate (MAC) unit based on the Urdhva- Tiryakbhyam sutra within the Arithmetic Logic Unit (ALU). The proposed architecture supports a simplified instruction set and enables parallel partial product generation, thereby enhancing throughput and energy efficiency. The processor is described using Verilog HDL and validated through simulation and synthesis, demonstrating improved performance over conventional RISC architectures. The invention is particularly suitable for embedded systems, signal processing, and VLSI applications requiring high speed and low power operation.
Disclaimer: Curated by HT Syndication.
