MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202641101773 A) filed by Vellore Institute Of Technology on August 23, 2026, for A Hardware-Accelerated Distributed Causal Memory System With Cryptographically Verified Dependency Compression.
Inventors include Anil Verma; Vedansh Gupta; and Saksham Gupta.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: A hardware-accelerated distributed causal memory system (100) comprises a hardware-accelerated causal register implemented in volatile memory, a hardware telemetry monitoring module, a dependency pruning module, a cryptographic verification module, and a persistent storage management module. The hardware-accelerated causal register intercepts incoming transaction events and constructs a directed acyclic causal graph representing causal dependency relationships. The hardware telemetry monitoring module continuously monitors processor cache utilization, persistent storage latency, and network buffer conditions to generate hardware- trigger information. Upon detection of predefined hardware thresholds, the dependency pruning module identifies redundant intermediate dependency states and performs recursive dependency compression. The cryptographic verification module computes cryptographic hash values for removed dependency states and generates cryptographically verified dependency vectors connecting remaining dependency states. The persistent storage management module stores the compressed causal graph in persistent storage. Historical dependency states are reconstructed through traversal of the stored dependency vectors and verification of embedded cryptographic hash values.
Disclaimer: Curated by HT Syndication.
