MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641109357 A) filed by Agnit Semiconductors Private Limited on September 11, 2026, for A Co-Packaged Semiconductor Device For Improving Linearity Performance And A Method Thereof.
Inventors include Terirama Thingujam; Digbijoy Neelim Nath; and Hareesh Chandrasekar.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: A CO-PACKAGED SEMICONDUCTOR DEVICE FOR IMPROVING LINEARITY PERFORMANCE AND A METHOD THEREOF The present invention relates to a co-packaged semiconductor device (100) for improving linearity performance and a method (400) thereof. The co-packaged semiconductor device (100) comprises an input terminal (102), a common gate interconnection node (104), a plurality of transistor dies including a first transistor die (106) and a second transistor die (108) exhibiting different threshold voltages, a common drain interconnection node (112), and an output terminal (114). The common gate interconnection node (104) distributes an electrical input signal to the plurality of transistor dies electrically interconnected in a parallel configuration. The plurality of transistor dies amplify the electrical input signal according to their respective threshold voltages to collectively generate a composite transconductance response exhibiting improved linearity. The common drain interconnection node (112) combines electrical outputs generated by the plurality of transistor dies to provide a combined electrical output through the output terminal (114). FIG. 1
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