MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202641062236 A) filed by St. Peter's Engineering College; A Narmada; Dr K Viswanath Allamraju; Arikatla Sireesha; Dr. Venkateswarulu Naik. B; Dr. G. Deepthi; Malla Reddy Deemed To Be University; Bhargavi Marri; Raman Kumar M; and Poluri Saranya, Hyderabad, Telangana, on May 16, for 'ultra-low power neuromorphic vlsi architecture for real-time edge intelligence processing.'
Inventor(s) include Guna Hari Keerthana; A Narmada; Dr K Viswanath Allamraju; Arikatla Sireesha; Dr. Venkateswarulu Naik. B; Dr. G. Deepthi; Dr G Prasanna Kumar; Bhargavi Marri; Raman Kumar M; and Poluri Saranya.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "The present invention discloses an ultra-low power Very Large Scale Integration (VLSI) architecture specifically engineered for neuromorphic computing to facilitate real-time edge intelligence processing. Conventional Von Neumann computing architectures suffer from the "memory wall" bottleneck, where the constant data transfer between the central processing unit and memory leads to high power consumption and significant latency. The invention overcomes these limitations by providing a non-Von Neumann infrastructure that mimics the biological brain's parallel processing capabilities, integrating memory and computation within specialized synaptic crossbar arrays. The system architecture utilizes an asynchronous spiking neural network (SNN) framework that processes information through discrete events or "spikes," rather than continuous data streams. Traditional digital signal processors frequently consume excessive power by maintaining active clock cycles even during idle periods, whereas the proposed neuromorphic model leverages event-driven activation to ensure that energy is only expended when a significant input trigger is detected. This sparse-coding approach ensures that the silicon area is utilized with maximum energy efficiency, enabling high-performance AI inference on battery-constrained edge devices such as wearables and remote industrial sensors. The invention further incorporates a reconfigurable synaptic weight module that allows for on-chip learning and adaptation to local data variations without requiring a connection to a central cloud server. By utilizing sub-threshold analog circuits and specialized memristive elements, the framework provides a robust solution for real-time pattern recognition and anomaly detection. The result is a proactive hardware engine that significantly reduces the carbon footprint of AI processing, ensuring that intelligent decision-making is localized at the point of data acquisition with milliwatt-scale power requirements. Furthermore, the system integrates a decentralized communication fabric based on Address Event Representation (AER), which allows multiple neuromorphic cores to synchronize their activities through a high-speed asynchronous bus. This capability ensures that the architecture can scale to accommodate complex deep learning models while maintaining a low-power profile. By maintaining a dynamic mapping of neural connectivity, the invention provides an adaptive hardware solution that supports the development of future-proof autonomous systems and intelligent IoT infrastructures. Finally, the invention provides a modular design interface that allows for the simultaneous processing of diverse sensory inputs, including visual, auditory, and tactile data, through a unified spike-domain representation. This architecture enables edge devices to standardize their intelligence benchmarks, allowing for the minimization of latency in safety-critical applications like autonomous navigation. By utilizing automated circuit-level optimization and leak-current mitigation techniques, the invention ensures that high-priority intelligence tasks are executed with zero-compromise efficiency and forensic accuracy."
Disclaimer: Curated by HT Syndication.
