Intellectual Property India Publishes Patent Application for 'Technique For Generating A Bounding Volume Hierarchy' Filed by Advanced Micro Devices, Inc.

MUMBAI, India, Aug. 22 -- Intellectual Property India has published a patent application (202517054899 A) filed by Advanced Micro Devices, Inc., Santa Clara, U.S.A., on June 6, for 'technique for generating a bounding volume hierarchy.'

Inventor(s) include Tsakok, John Alexandre.

The application for the patent was published on Aug. 22, under issue no. 34/2025.

According to the abstract released by the Intellectual Property India: "A technique for building a bounding volume hierarchy is disclosed. The technique subdividing a candidate box node based on a resolution to generate a plurality of cells of the candidate box node; identifying a plurality of nodes of a triangle set collection that fit within the cells; generating a plurality of candidate splits based on the plurality of nodes; selecting a candidate split based on a selection criterion to obtain a selected candidate split; and generating child box nodes for a box node of a bounding volume hierarchy under construction, based on the selected candidate split."

The patent application was internationally filed on Nov. 27, 2023, under International application No.PCT/US2023/081182.

Disclaimer: Curated by HT Syndication.