MUMBAI, India, April 17 -- Intellectual Property India has published a patent application (202641043577 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on April 6, for 'system for assertion-level verification of handwritten mathematical proofs using logic conversion.'
Inventor(s) include Sujatha R; Dheeraj Sutram; Tanmay Aaglave; and Akshat Pandey.
The application for the patent was published on April 17, under issue no. 16/2026.
According to the abstract released by the Intellectual Property India: "System for Assertion-Level Verification of Handwritten Mathematical Proofs Using Logic Conversion. The present invention discloses a system for assertion-level verification of handwritten mathematical proofs by integrating handwriting recognition, structured representation, logical conversion, and automated verification. The system captures handwritten mathematical expressions and converts the same into an Abstract Syntax Tree preserving spatial and semantic relationships. A logic conversion module transforms the structured representation into Boolean assertions representing logical implications between successive proof steps. A verification engine evaluates the assertions using a Computer Algebra System and a predefined library of mathematical axioms. An intention analysis module analyzes proof history and contextual indicators to distinguish between unintentional computational errors and intentional logical contradictions. A user interface module provides context-aware feedback indicating validity, errors, or contradictions directly on the handwritten input. The system enables real-time semantic validation while preserving natural handwritten proof workflows."
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