MUMBAI, India, Jan. 23 -- Intellectual Property India has published a patent application (202521095660 A) filed by Persistent Systems, Pune, Maharashtra, on Oct. 6, 2025, for 'system and method for uncertainty-aware, validator-gated, proof- carrying code generation with policy-bound retrieval and contradiction detection.'
Inventor(s) include Mr. Nitish Shrivastava; and Mr. Pradeepkumar Sharma.
The application for the patent was published on Jan. 23, under issue no. 04/2026.
According to the abstract released by the Intellectual Property India: "A computer-implemented system orchestrates multi-stage code generation using an external Semantic State Machine (SSM) Controller and validator-gated progression. Each stage yields Proof-Carrying Code Artifacts (PCCA) embedding executable contracts, test seeds, coverage, mutation scores, symbolic traces, SBOM, and Merkle attestations. The controller advances only 10 under Uncertainty-Aware Gating (UAG) where each validator returns calibrated score and uncertainty bound; acceptance requires meeting score thresholds and confidence thresholds. The system performs Counterfactual Falsification for Programs (CFS-P) combining property-based testing, concolic execution, fuzzing, mutation testing, and complexity falsification. External references are selected by Policy-Bound Retrieval for Tech (PBR-T) via constrained optimization 15 respecting API version windows, freshness, licensing, and CVE policies. Validation resources are scheduled by Validator Bandits (VB-Code) to minimize acceptance uncertainty per compute cost. Failures trigger Semantic De-Oscillation for Code (SDD-Code) that computes minimal typed-AST patches to satisfy failed constraints. The approach reduces hallucination, ensures security, and delivers reproducible, enterprise-grade code with cryptographic provenance."
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