MUMBAI, India, Feb. 27 -- Intellectual Property India has published a patent application (202621003905 A) filed by Mr. Panthagani Vijaya Babu; Dr. Sonal Yadav; and Dr. Vijay Holimath, Raipur, Chhattisgarh, on Jan. 14, for 'system and method for kernel-based hardware acceleration of symbolic computation.'
Inventor(s) include Mr. Panthagani Vijaya Babu; Dr. Sonal Yadav; and Dr. Vijay Holimath.
The application for the patent was published on Feb. 27, under issue no. 09/2026.
According to the abstract released by the Intellectual Property India: "System and Method for Kernel-Based Hardware Acceleration of Symbolic Computa-tion Abstract of the Invention The present invention relates to a symbolic-hardware integration framework for accelerat-ing arithmetic operations in symbolic computation environments, such as Wolfram Mathe-matica, using a RacEr manycore FPGA platform. The framework comprises a host-side ab-straction layer that intercepts symbolic arithmetic expressions and a lightweight loader API that marshals input data and manages execution of a computation-specific RacEr kernel. The kernel, compiled into a RISC-V binary, implements a CUDA-Lite execution model with grid-tile decomposition, strided threadloop distribution, hardware tile-group barriers, and modular device-math hooks for executing arithmetic operations. This design enables trans-parent offloading of computations, automatic data partitioning, and deterministic parallel execution without user intervention or dependency on CUDA/OpenCL runtimes. The system preserves symbolic semantics, provides flexible arithmetic behavior, achieves high compu-tational throughput, and ensures efficient utilization of FPGA resources, thereby bridging the gap between symbolic programming environments and high-performance hardware acceler-ation."
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