MUMBAI, India, April 17 -- Intellectual Property India has published a patent application (202641043696 A) filed by Indian Institute Of Science; and Indian Space Research Organisation, Bengaluru, Karnataka, on April 6, for 'system and method for encoding of non-binary quasi-cyclic low-density parity-check codes.'
Inventor(s) include G M, Karthik Bharadwaj; Venkataramanappa, Suresh Kumar; Kumar, Pavan; Mishra, Deepak; and Garani, Shayan Srinivasa.
The application for the patent was published on April 17, under issue no. 16/2026.
According to the abstract released by the Intellectual Property India: "A system (200) for non-binary quasi-cyclic low-density parity-check codes is disclosed. The system (200) includes a processor (202) in communication with a memory (208). The processor constructs a parity-check matrix (204) having a quasi-cyclic block-circulant structure with block-rows and block-columns and derives a systematic generator matrix comprising an identity portion and a parity submatrix portion. An encoder (210) receives the systematic generator matrix and stores the parity submatrix portion. The encoder comprises a multiplier bank (212) coupled to a barrel shifter (214) and the memory, configured to multiply the parity submatrix portion and input message symbols to produce partial products. An exclusive-OR array (216) generates parity symbols by accumulating the partial products. A controller is coupled to the memory, multiplier bank, barrel shifter, and XOR array, coordinating the encoding operation."
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