MUMBAI, India, April 17 -- Intellectual Property India has published a patent application (202641043304 A) filed by Bapatla Surendra Babu; and Irukumalli Priyanka, Tenali, Andhra Pradesh, on April 4, for 'substrate-coupled mesh clock distribution apparatus exploiting electromagnetic phase-locking for jitter reduction.'
Inventor(s) include Bapatla Surendra Babu; and Irukumalli Priyanka.
The application for the patent was published on April 17, under issue no. 16/2026.
According to the abstract released by the Intellectual Property India: "A clock distribution apparatus executes collective phase-locking and jitter reduction across integrated circuits. A conventional hierarchical clock tree (310) suffers from random walk accumulation (320). The proposed solution provides a 2D clock buffer mesh network (120) comprising clock buffer nodes (130) deployed on a bulk semiconductor substrate (110). The layout features the controlled omission of isolation structures (150), lacking protective guard rings. This establishes robust nearest-neighbor electromagnetic coupling (210) between nodes sharing a common clock frequency. This attains a coupling level sufficient to induce mutual phase-locking behavior (230), driving synchronization dynamics (220) that force the network into collective phase alignment (240). This mutual injection-locking enforces collective jitter suppression (330), achieving relative timing variability reduction (340). By exploiting substrate coupling, the apparatus enables architectural area recovery (420) of silicon wasted on isolation structures. It is principally used to stabilize massive multi-core SoC clock distribution networks."
Disclaimer: Curated by HT Syndication.
