Intellectual Property India Publishes Patent Application for 'Risc-V Processor Architecture With Tiered-Memory Isa Extension, Tier-Aware Translation Lookaside Buffer, And Thunderbolt-Attached External Dram Expansion With Risc-V Bridge Controller For Linux-Based Heterogeneous Memory Systems' Filed by Mr. Jyotiprakash Mishra

MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202631036815 A) filed by Mr. Jyotiprakash Mishra, Bhubaneswar, Odisha, on March 26, for 'risc-v processor architecture with tiered-memory isa extension, tier-aware translation lookaside buffer, and thunderbolt-attached external dram expansion with risc-v bridge controller for linux-based heterogeneous memory systems.'

Inventor(s) include Mr. Jyotiprakash Mishra; Prof. Sanjay K. Sahay; Ms. Swati Mishra; and Mr. Aman Pathak.

The application for the patent was published on May 29, under issue no. 22/2026.

According to the abstract released by the Intellectual Property India: "A three-layer architecture for heterogeneous memory systems comprising: (1) a RISC-V ISA extension (Xmtier) defining tier-aware load/store instructions (LD.TIER, SD.TIER), a hardware page migration instruction (MIGRATE), a tier statistics instruction (TIERSTAT), and a load-wait instruction (LWAIT), with a tier-aware TLB (700) extending page table entries with a tier field, an asynchronous load queue (800) for non-blocking high-latency memory access, and a hardware page migration engine (900) that substantially accelerates page migration compared to software; (2) a Thunderbolt-attached external DRAM expansion device built around a RISC-V bridge controller SoC (200) with custom DDR5 instructions (DDRSEQ, DDRREFRESH, DDRTRAIN), a latency-compensating cache (300) with a write-snoop invalidation protocol (WSIP) for cache coherence and firmware-driven prefetch, and DDR5 memory module interfaces; and (3) a Linux kernel module (400) leveraging the Xmtier extension for dynamic ACPI SRAT/HMAT injection, NUMA node registration, hardware-accelerated page migration, and hot-plug lifecycle management. Multi-port Thunderbolt bandwidth aggregation (500) increases aggregate bandwidth by address-interleaved striping across multiple ports. The invention enables RISC-V processors to transparently utilise Thunderbolt-attached DRAM for memory-intensive workloads with ISA-level support for heterogeneous memory tiering."

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