MUMBAI, India, Feb. 6 -- Intellectual Property India has published a patent application (202541126582 A) filed by Pace Institute Of Technology And Sciences, Vijayawada, Andhra Pradesh, on Dec. 14, 2025, for 'real time eeg artifact suppression vlsi asic with adaptive blind source separation - hardware chip that cleans eeg signals on the fly..'
Inventor(s) include S. Ch. Kantharao; B. Vijaya; Dr M Apparao; G. Vijay Kiran; and Dr. Vijayachandra Kavuri.
The application for the patent was published on Feb. 6, under issue no. 06/2026.
According to the abstract released by the Intellectual Property India: "The invention discloses a Very Large Scale Integration (VLSI) Application-Specific Integrated Circuit (ASIC) for real-time suppression of artifacts in electroencephalogram (EEG) signals using adaptive blind source separation. The ASIC integrates an analog front-end, digital signal preprocessing, and a hardware-implemented adaptive engine based on techniques such as online recursive independent component analysis. Multi-channel EEG inputs are continuously processed: whitened, separated into independent components, artifactual sources (e.g., ocular, muscular) automatically detected and suppressed using feature-based criteria, and clean neural signals reconstructed with minimal latency and power consumption. Designed in CMOS technology, the chip enables low-power ( 5 mW), portable, real-time EEG cleaning without offline processing or external computation. This facilitates applications in wearable brain-computer interfaces, clinical monitoring, epilepsy detection, and neurofeedback. Advantages over prior art include hardware acceleration for non-stationary signals, dynamic adaptation, and preservation of brain signal integrity, overcoming limitations of software-based methods in power, speed, and portability. The invention significantly enhances EEG signal quality on-the-fly, improving diagnostic accuracy and usability in real-world scenarios."
Disclaimer: Curated by HT Syndication.
