MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202631036816 A) filed by Mr. Jyotiprakash Mishra, Bhubaneswar, Orissa, on March 26, for 'programmable instruction fusion engine with sram-based rules table for risc-v iot processors.'
Inventor(s) include Mr. Jyotiprakash Mishra; Prof. Sanjay K. Sahay; Ms. Swati Mishra; and Mr. Aman Pathak.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "A programmable instruction fusion mechanism for RISC-V processors comprising a Fusion Detection Unit (120) positioned between a fetch buffer (115) and a decode unit (130). The Fusion Detection Unit includes an SRAM-based rules table (122) storing fusion rule entries that specify instruction patterns and register dependency requirements for fusible instruction pairs. A parallel match logic array (124) compares consecutive instruction pairs against all rule entries simultaneously in a single clock cycle. When a match is detected, a fused micro-operation generator (126) emits a single internal operation encoding both original instructions, reducing pipeline bandwidth and energy consumption. The SRAM-based storage enables runtime modification of fusion rules through a Control-and-Status Register interface without hardware changes. A banked rules table architecture supports zero-overhead switching between workload-specific fusion rule sets during context switches, making the invention particularly suitable for Internet-of-Things processors that execute diverse workloads including sensor processing, cryptography, and communication protocols."
Disclaimer: Curated by HT Syndication.
