MUMBAI, India, Aug. 8 -- Intellectual Property India has published a patent application (202421008333 A) filed by Dhirubhai Ambani Institute Of Information And Communication Technology, Gandhinagar, Gujarat, on Feb. 7, 2024, for 'programmable high voltage, low noise analogue/mixed signal bias driver asic".'
Inventor(s) include Rutu Mahendrabhai Parekh; Radhika Agrawal; Viraj Panchal; and Rupali Patel.
The application for the patent was published on Aug. 8, under issue no. 32/2025.
According to the abstract released by the Intellectual Property India: "The present invention relates to a programmable high voltage integrated bias driver apparatus (100). The apparatus includes an input shift register and control unit (101) that generates a control signal and parallel data synchronized with a clock signal. The bias driver (100) comprises multiple bias channels, each loaded with the parallel data. Each bias channel includes a first register connected to the input shift register and control unit (101) to receive the parallel data, and a second register connected to the first register. The second register receives the parallel data from the first register along with a SET/RESET signal. A current steering segmented DAC is connected to the second register to convert the parallel data into an analog output signal. Additionally, a high voltage operational amplifier (Op-Amp) is operatively connected to the current steering segmented DAC to enhance the output signal."
Disclaimer: Curated by HT Syndication.
