MUMBAI, India, April 20 -- Intellectual Property India has published a patent application (202514091110 A) filed by Nokia Solutions And Networks Oy, Espoo, Finland, on Sept. 23, 2025, for 'processor architecture for processing multiple instructions in parallel.'
Inventor(s) include Borghs, Eric; and Jivanescu, Mihaela Andreea.
The application for the patent was published on April 17, under issue no. 16/2026.
According to the abstract released by the Intellectual Property India: "A processor comprising: a program memory for storing instructions; a decoder adapted to convert the instructions into respective operation codes and enable signals; a controller including an instruction word consisting of a plurality of instruction slots for providing the instructions to the decoder; a plurality of processing elements, each processing element being configured to operate during a time slot in accordance with an 10 operation code provided to an input of the considered processing element so as to apply a mathematical operation to an input data element and generate an output data element, wherein an instruction provided via an instruction slot identifies one or more target processing elements to be used for executing the considered instruction, wherein the enable signals are adapted to control assignment of the operation codes to the processing 15 elements; interconnection circuitry adapted to provide any of the operation codes to any of the processing elements at each time slot and configured to be operated in accordance with the enable signals."
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