MUMBAI, India, Feb. 6 -- Intellectual Property India has published a patent application (202641006904 A) filed by Dr. Manju Somanath; Dr. J. Kannan; Dr. V. Sangeetha; Dr. J. Mahalakshmi; Dr. M. Cruz; Dr. A. Mydeen Bibi; Dr. V. Krithika; and Dr. P. Vijaya Shanthi, Trichy, Tamil Nadu, on Jan. 23, for 'prime-residue adaptive hardware clock for ultra-secure time synchronization.'
Inventor(s) include Dr. Manju Somanath; Dr. J. Kannan; Dr. V. Sangeetha; Dr. J. Mahalakshmi; Dr. M. Cruz; Dr. A. Mydeen Bibi; Dr. V. Krithika; and Dr. P. Vijaya Shanthi.
The application for the patent was published on Feb. 6, under issue no. 06/2026.
According to the abstract released by the Intellectual Property India: "Prime-Residue Adaptive Hardware Clock for Ultra-Secure Time Synchronization A hardware-based time synchronization device employing prime-residue adaptive clocking is disclosed. The device generates clock ticks based on modular residues derived from dynamically selected prime numbers, wherein residue progression governs variable time-step increments while preserving long-term temporal accuracy. A synchronization protocol aligns residue evolution between communicating devices, enabling secure and tamper-resistant time synchronization. The non-uniform external timing pattern significantly reduces susceptibility to spoofing, replay, and desynchronization attacks while maintaining precise internal timekeeping. By embedding number-theoretic behavior directly into clock hardware, the invention provides intrinsic security against timing manipulation without reliance on external references or software-based correction. The invention is applicable to telecommunications, financial systems, distributed computing, and industrial control environments requiring ultra-secure and resilient time synchronization."
Disclaimer: Curated by HT Syndication.
