MUMBAI, India, Feb. 27 -- Intellectual Property India has published a patent application (202541067598 A) filed by Indian Institute Of Technology, Chennai, Tamil Nadu, on July 15, 2025, for 'optimized grid based interpretable self organizing map with a coverage based performance metric.'

Inventor(s) include Ramu, Palaniappan; and Khalid, Mohd Aman.

The application for the patent was published on Feb. 27, under issue no. 09/2026.

According to the abstract released by the Intellectual Property India: "Techniques for enhancement of initial neuron grid selection for interpretable 5 Self-Organizing Map (iSOM) are described. The method introduces a Distance Coverage Score (DCS) and Data Inclusion Score (DIS) to assess pre-training neuron layout alignment and design space coverage. A Coverage-Based Performance Metric (CBPM) is computed from these scores, capturing both distance proximity between neurons and the design 10 space, and topological inclusion of the neuron manifold. The CBPM serves as an objective function in an optimization-driven strategy to determine an initial iSOM grid configuration. This approach may result in a well-distributed neuron grid that captures the shape and extent of the underlying Design of Experiments (DoE) sample space, potentially improving iSOM 15 interpretability and performance in various applications."

Disclaimer: Curated by HT Syndication.