Intellectual Property India Publishes Patent Application for 'Optimal Test Point Insertion For Enhanced Small Delay Defect Coverage' Filed by Vellore Institute Of Technology

MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541122895 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on Dec. 5, 2025, for 'optimal test point insertion for enhanced small delay defect coverage.'

Inventor(s) include Sivanantham S; and Mr. Faraz Aatif.

The application for the patent was published on Jan. 2, under issue no. 01/2026.

According to the abstract released by the Intellectual Property India: "The present disclosure provides a test point insertion system (300) for enhancing small delay defect coverage in digital circuits. The system (300) includes a timing analysis module (302) that performs static timing analysis on gate-level netlists and extracts timing slack values, a fault processing module (310) that executes automatic test pattern generation and filters delay faults based on a slack difference criterion where minimum slack is less than 50% of actual slack, and a test point generator (318) that inserts control points at nodes with high slack values and high fanout characteristics to improve delay test coverage. The timing analysis module (302) includes PrimeTime STA (304), slack analyzer (306), and path extractor (308). The fault processing module (310) includes ATPG engine (312), fault filter (314), and node selector (316). The test point generator (318) includes control point inserter (320), netlist modifier (322), and SDF generator (324)."

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