Intellectual Property India Publishes Patent Application for 'Neural Engine With Accelerated Multipiler-Accumulator For Convolution Of Intergers' Filed by Apple Inc.

MUMBAI, India, Oct. 31 -- Intellectual Property India has published a patent application (202517093642 A) filed by Apple Inc., Cupertino, U.S.A., on Sept. 29, for 'neural engine with accelerated multipiler-accumulator for convolution of intergers.'

Inventor(s) include Wang, Lei; Shin, Jaewon; Lee, Seungjin; Song, Ji Liang; Liu, Michael L.; and Mills, Christopher L.

The application for the patent was published on Oct. 31, under issue no. 44/2025.

According to the abstract released by the Intellectual Property India: "Embodiments of the present disclosure relate to a multiply-accumulator circuit that includes a main multiplier circuit operable in a floating-point mode or an integer mode and a supplemental multiplier circuit that operates in the integer mode. The main multiplier circuit generates a multiplied output that undergoes subsequent operations including a shifting operation in the floating-point mode whereas the supplemental multiplier generates another multiplied output that does not undergo any shifting operations. Hence, in the integer mode, two parallel multiply-add operations may be performed by the two multiplier circuits, and therefore accelerate the multiply-adder operations. Due to the lack of additional shifters associated with the supplemental multiplier circuit, the multiply-accumulator circuit does not have a significantly increased footprint."

The patent application was internationally filed on Mar. 15, 2024, under International application No.PCT/US2024/020190.

Disclaimer: Curated by HT Syndication.