MUMBAI, India, April 17 -- Intellectual Property India has published a patent application (202641042472 A) filed by Indian Space Research Organization, Bangalore, Karnataka, on April 2, for 'methodologies/processes for capturing defects at gate level in silicon based mos and bipolar semiconductor devices.'
Inventor(s) include Sarat Kumar Dash; Md. Nazrul Islam; and C Ramachandra.
The application for the patent was published on April 17, under issue no. 16/2026.
According to the abstract released by the Intellectual Property India: "The work describes methodologies / processes for capturing buried/hidden defects / contamination / structural damages at gate level in a silicon-based MOS and Bipolar semiconductor device. Generally, gate level lies several microns below the top surface. Gate level is embedded below passivation layer, metal layer and oxide layer. These defects cannot be seen from the surface using optical or electron or Ion microscope. The processes use controlled delayering of passivation layer, metal layers and oxide layers. Control of temperature, chemical concentration and etch time are critical in these processes. The processes need to ensure that gate level structures are not damaged. It is important to retain the original defects. At the same time the processes need to ensure that new / additional defects are not introduced."
Disclaimer: Curated by HT Syndication.
