UMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541125279 A) filed by B V Raju Institute Of Technology, Narsapur, Telangana, on Dec. 11, 2025, for 'method for reducing computational cost in quantum circuits via gate optimization.'
Inventor(s) include Mummadi Swathi; S Akshaya; D Rohitha; and G Srinath.
The application for the patent was published on Jan. 2, under issue no. 01/2026.
According to the abstract released by the Intellectual Property India: "Efficient quantum gate optimization is essential for enabling practical and scalable quantum computing, particularly on today's noisy, resource-constrained quantum hardware. This work presents a comprehensive study of optimization strategies for quantum circuits built using the Clifford+T gate set, emphasizing the reduction of T-gate count one of the most expensive operations in fault-tolerant quantum computation. In addition to T-gate minimization, the study focuses on lowering circuit depth and reducing ancillary qubit overhead, both of which directly influence circuit reliability and execution fidelity. By leveraging techniques such as gate fusion, gate cancellation, qubit reordering, and optimal synthesis of phase, Hadamard, and multi-controlled gates, we explore methods that significantly minimise resource cost without compromising computational accuracy. The effectiveness of these strategies is analysed through applications to circuits used in Grover's search, quantum arithmetic, and comparator designs. Simulation-based evaluations demonstrate that systematic gate-level optimization substantially reduces decoherence effects, enhances noise resilience, and improves overall circuit robustness. The findings contribute valuable insights toward building cost-efficient, fault-tolerant, and scalable quantum circuits suitable for near-term and future quantum hardware."
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