MUMBAI, India, June 13 -- Intellectual Property India has published a patent application (202517049489 A) filed by Schaeffler Technologies Ag & Co. Kg, Herzogenaurach, Germany, on May 22, for 'method and system with a multi-core microcontroller with chained task and offload logic.'
Inventor(s) include Eloy, Stephane; and Delpech, Franck.
The application for the patent was published on June 13, under issue no. 24/2025.
According to the abstract released by the Intellectual Property India: "The invention relates to a method implemented in a multi-core microcontroller with a first core and a second core, the method comprising: - defining a recurring chained task that can be executed by parts on the first and second cores, with a nominal implementation associated with a reference distribution of the parts over the different cores, the second core requiring a second latency delay (DL2) to take on a second part (TK2) of the chained task; - estimating a current value of the second latency delay; - if the current value of the second latency delay is greater than a first threshold value (DS2a), then activating an offloading mode of the second core for which a head portion of the second part is executed on the first core and deactivated on the second core; and - if the value of the second latency delay is less than a second threshold value, returning to the nominal implementation."
The patent application was internationally filed on Nov. 21, 2023, under International application No.PCT/EP2023/082457.
Disclaimer: Curated by HT Syndication.
