MUMBAI, India, Oct. 11 -- Intellectual Property India has published a patent application (202517089661 A) filed by Arm Limited, Cambridge, U.K., on Sept. 19, for 'matrix multiplication in a dynamically spatially and dynamically temporally dividable architecture.'
Inventor(s) include Beu, Jesse; and Grocutt, Thomas.
The application for the patent was published on Oct. 10, under issue no. 41/2025.
According to the abstract released by the Intellectual Property India: "A data processing apparatus includes first vector registers and second vector registers, both dynamically spatially and dynamically temporally dividable. Decode circuitry receives one or more matrix multiplication instructions that indicate a set of first elements in the first vector registers and a set of second elements in the second vector registers, and in response to receiving the matrix multiplication instructions they generate a matrix multiplication operation. The matrix multiplication operation causes one or more execution units to perform a matrix multiplication of the set of first elements by the set of second elements and an average bit width of the first elements is different to an average bit width of the second elements."
The patent application was internationally filed on Jan. 31, 2024, under International application No.PCT/GB2024/050262.
Disclaimer: Curated by HT Syndication.
