MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541122993 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on Dec. 5, 2025, for 'machine learning based power estimation system for vlsi circuits.'
Inventor(s) include Dr. Sakthivel Ramachandran; and Mr. Maniyar Mohammed Saqlain.
The application for the patent was published on Jan. 2, under issue no. 01/2026.
According to the abstract released by the Intellectual Property India: "The present disclosure provides a VLSI Power Estimation System (800) for digital VLSI circuits. The system includes a Dataset Generation Module (802) that synthesizes Verilog HDL code using a Quartus Synthesis Engine (804) and extracts power measurements using a Power Analyzer Tool (806). A Feature Extractor (808) derives synthesis-level features including gate count, logic depth, switching activity, net count, and operating frequency. A Machine Learning Framework (810) includes a Model Training Engine (812) that trains regression algorithms (Linear Regression, Decision Tree, Random Forest, Gradient Boosting, and XGBoost), a Performance Evaluator (814) that calculates Root Mean Squared Error and R-squared metrics, and a Model Selector (816) that identifies optimal algorithms. A Hardware Implementation Module (818) includes an HLS Converter (820) for synthesizable C++ code and an FPGA Deployment Unit (822) for Artix-7 FPGA implementation."
Disclaimer: Curated by HT Syndication.
